The present disclosure relates generally to semiconductor device manufacturing and, more particularly, to deep trench isolation of embedded DRAM (eDRAM) to improve latch-up immunity.
In the integrated circuit (IC) industry, manufacturers are embedding dynamic random access memory (DRAM) arrays on the same substrate as microprocessor cores or other logic devices. This technology is commonly referred to as embedded DRAM (eDRAM). Embedded DRAM provides microcontrollers and other logic devices with faster access to larger capacities of on-chip memory at a lower cost than other currently available systems having conventional embedded static random access memory (SRAM) and/or electrically erasable programmable read only memory (EEPROM).
The structural requirements and process steps used in forming logic devices (e.g., flip-flops, inverters, etc.) are generally not compatible with the structural requirements and processing steps of a DRAM cell. For example, logic devices generally benefit from having higher doped source and drain regions, whereas DRAM cells generally benefit from lighter doped source and drain regions. Moreover, as integrated semiconductor devices continue to grow in complexity, there is a constant need to increase the density of the devices. This increase in density can create several problems, particularly with eDRAM devices, that can lead to device failure if not addressed. One such problem stems from the propensity for some semiconductor devices, such as those included in CMOS circuitry, to “latch-up.” Latch-up is a well known problem triggered by certain electrical conditions acting upon unwanted parasitic bipolar transistors contained in the device structure.
More specifically, latch-up is typically caused by the close proximity of n-channel and p-channel elements in modern CMOS devices. For example, a typical CMOS device fabricated on a p-type substrate would contain a p-channel element fabricated in a n-well (or n-type region) and an n-channel element fabricated in a p-well (or p-type region), with only a short distance between the wells. This structure inherently forms a parasitic lateral bipolar structure (npn) and parasitic vertical bipolar structure (pnp). Under certain biasing conditions, the pnp structure can supply base current to npn structure (or vice versa), thereby causing a large current to flow from one well to the other well. This large current creates excessive heat which can subsequently damage the CMOS device.
The propensity for CMOS devices to latch-up has been addressed in several ways. One conventional method for suppressing latch-up involves the implantation of heavily doped regions (e.g., with boron ions in the p-well, or phosphorous ions in the n-well) at high implantation energies. The introduction of the higher concentration dopants serves to reduce the substrate/well resistance, thereby decreasing the tendency for a parasitic vertical transistor to turn on. However, as a result of these high dose/high energy implants, crystal defects may be generated in the implantation (CMOS) area and propagated relatively long distances, possibly even into a neighboring array of embedded DRAM storage cells. The propagated defects, in turn, can increase the junction leakage of the less tolerant DRAM cells and thereby negatively impact the data retention time of those cells. Accordingly, it is desirable (especially in view of continued device miniaturization) to continue to improve CMOS latch-up immunity without degrading DRAM retention time.